Cadence Maestro Brings NVIDIA AI Models to Chip Design

Cadence Design Systems has introduced Maestro, a suite of NVIDIA-backed AI models designed to support semiconductor engineering. Chipmakers can deploy the models on their own infrastructure or through cloud platforms. The launch highlights growing competition to use AI in chip design, with Cadence focusing on flexible deployment and engineering-specific tools.
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Written By:
Soham Halder
Reviewed By:
Achu Krishnan
Published on: 
Updated on: 

Cadence Design Systems has introduced a new portfolio of AI models to help engineers develop computer chips faster. The new suite, called Cadence Maestro, uses NVIDIA technology and lets semiconductor companies run AI tools in their own data centers instead of relying entirely on external cloud services.

The launch deepens Cadence’s partnership with NVIDIA as chip design software companies race to bring AI agents into engineering workflows. The first Maestro models are expected to reach select early-access customers in the fourth quarter of 2026.

Cadence Maestro Targets Chip Design Work

Designing modern chips means arranging billions of transistors while meeting strict performance, power, and cost targets. Cadence wants Maestro to help engineers handle parts of this complex process using AI agents that can generate designs, evaluate results, and support technical decisions.

The portfolio is built partly on NVIDIA’s open-weight Nemotron model and uses NVIDIA’s OpenShell security technology. Cadence combines these models with its electronic design automation tools and engineering expertise to create AI systems focused on semiconductor and system design.

According to Cadence, early tests show up to 30% higher output quality and up to five times greater token efficiency than general-purpose AI models. These are company-reported results, and actual performance may vary by task and deployment.

Chipmakers Can Keep AI Inside Their Own Systems

One of Maestro’s key features is deployment flexibility. Customers can use the models through Cadence’s cloud platform, public cloud services or their own infrastructure behind corporate firewalls.

This option could appeal to semiconductor companies that handle sensitive chip designs and proprietary engineering data. Keeping AI systems in-house may give them greater control over how information is accessed and processed.

Companies can also fine-tune the models using their own chip designs and workflows. This could help AI agents produce results that better match specific engineering requirements, although customers will still need to evaluate performance and security before using them in production.

Cadence Takes a Different Route from Synopsys

Cadence’s launch comes as its rival Synopsys develops GPT-Synopsys through a partnership with OpenAI. That model is planned to run on OpenAI-hosted infrastructure, highlighting a different approach to AI deployment in chip design.

Cadence says Maestro is designed to work with different AI models, including both open-weight and proprietary systems. The company has also indicated that collaboration with commercial AI developers remains part of its broader strategy.

Also Read: NVIDIA's Vera CPUs Attract Modal as Chip Rivalry Heats Up

AI Competition Moves into Semiconductor Design

The launch reflects a growing effort to use AI not just to write code or answer questions, but to handle complex engineering work. If these systems can reliably improve design quality and reduce development time, they could become valuable tools for semiconductor companies facing rising technical demands.

However, the benefits will depend on how well AI agents perform on real-world chip projects. Cadence’s early-access rollout should provide a clearer picture of their practical value.

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