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Innovation in processor design and power-efficient computing is defining the future of everything from mobile devices to AI-powered systems. At the core of this transformation lies the intersection of performance, scalability, and customization, particularly in RISC-V and ARM-based architectures. These platforms have emerged to facilitate applications with a specific task such as Neural Network Processing, Embedded Systems, and Edge Computing. With companies all looking for silicon differentiation, there is a broad demand for specialized, energy-efficient Processor IP.
Karthik Wali stands at the forefront of this revolution, having built a career delivering cutting-edge semiconductor designs at global technology leaders including Amazon Lab126, LG Electronics Mobile Research, and Synopsys. Over the years, he has evolved from a design engineer into a senior contributor shaping next-generation IP architectures. “Processor IPs isn’t just about speed anymore,” he notes. “They must balance configurability, power efficiency, and intelligent instruction sets tailored for domain-specific workloads.”
At Amazon Lab126, Karthik contributed to neural network accelerator designs that relied on custom RISC-V co-processors. Convolution-heavy operations are IO-bound, consideration must be given to on-device AI performance, a factor which made the addition of complex instructions such as DW CONV2D a necessity and soon came with speedups of about 30%. In the past, he was a direct contributor to developing scalable RISC-V IPs at LG Electronics for floating-point acceleration and power-saving techniques such as dynamic clock gating. Non-trivial power savings of up to 20% on the SoC were achieved in these innovations while maintaining throughput levels.
With a holistic approach to IP and SoC design, he bridges gaps between silicon, firmware, and verification teams, ensuring seamless support for custom instructions and avoiding mismatches that commonly plague hardware/software co-development. In projects like LG’s Always-On IoT SoC platform, this integration allowed for dual ARC cores and specialized peripherals to work cohesively under aggressive power constraints.
Performance improvements have also come from process efficiency. By refining synthesis, linting, and power analysis workflows using tools like Genus, Spyglass, and Power Artist, Karthik helped reduce verification cycles by 20%, accelerating time-to-market for complex chips. His system-level insights were particularly evident in the optimization of System Level Cache (SLC) IPs, where innovations like way-shutdown and intelligent pipeline controls dramatically improved both performance and energy usage.
Beyond implementation, he shares his expertise through internal whitepapers and technical presentations. His paper “Designing High-Efficiency RISC-V Cores for Embedded ML” circulated within Amazon’s engineering teams, reflecting his deep understanding of the shifting role of processor IP in AI-driven products. “We’re seeing AI influence the core architecture of CPUs,” he explains. “Instruction sets are evolving to handle neural operations natively. The convergence is real.”
Looking ahead, Karthik sees RISC-V continuing to disrupt traditional processor licensing models due to its open nature. He anticipates a wave of flexible accelerators co-located with general-purpose cores, especially in embedded and edge devices where domain-specific computing is crucial. He also predicts that power efficiency, once an afterthought, will dominate architectural decisions as designers confront the limits of scaling.
Security, too, is top of mind. With increasing demands for tamper resistance and fault tolerance, Wali has worked on safety-enhanced cores with memory protection and ECC features, preparing systems for more stringent regulatory and user expectations. “It’s no longer about getting the job done, it’s about getting it done safely, efficiently, and intelligently,” he says.
Karthik Wali has proven himself a key player in the design of tomorrow’s intelligent silicon. His insights into scalability, architecture convergence, and design automation are shaping not just chips, but the future of computing.
