The future of semiconductor design is increasingly driven by chiplet architectures and the Universal Chiplet Interconnect Express (UCIe) standard, one of the key topics at the IEEE/JSAP Symposium on VLSI Technology and Circuits 2026. As the industry moves from building one large chip to combining multiple specialized chiplets in a single package, engineers are tackling new challenges in high-speed data transfer, power efficiency, and signal integrity. To explore how this shift is changing the way modern chips are designed, we spoke with Shreesha Hegde, a Senior Analog Design Engineer with extensive experience developing advanced semiconductor technologies for global leaders including Samsung and NXP Semiconductors. Throughout his career, he has developed several key technologies, including communication chips for the Samsung Galaxy Watch 7 and Galaxy Watch 8, UCIe intellectual property supporting next-generation chiplet architectures, and power-efficient NFC technologies for Ingenico payment terminals deployed worldwide. His work has helped advance high-speed connectivity, low-power analog and mixed-signal design, and semiconductor architectures used in millions of consumer electronics and payment devices.
I believe the biggest driver is complexity. For many years, the industry improved performance by making transistors smaller and fitting more functions onto a single chip. Today, AI, high-speed connectivity, and advanced consumer devices demand far more computing power, while users also expect longer battery life and faster performance. Building a single massive chip for every application is becoming less practical as designers balance performance, power, cost, and development time.
Chiplet architectures give engineers much more flexibility. Instead of redesigning an entire chip, we can combine specialized chiplets and optimize each one for a specific function. In my view, that approach helps companies innovate faster and respond more quickly to changing market needs. That's why I see chiplets and standards like UCIe becoming an important part of the next generation of semiconductor design.
In my experience, the biggest challenge is integration. While working on the communication chip for the Samsung Galaxy Watch, I saw how even small improvements in one part of the design could affect the performance and power efficiency of the entire system. Chiplet architectures create even more opportunities for optimization because engineers must design multiple specialized chiplets to operate as a single, efficient system.
For me, the key question is always how to improve performance without increasing power consumption. Whether it's Wi-Fi, Bluetooth, GPS, or a future chiplet-based system, users expect fast connectivity, smooth performance, and long battery life. Meeting those expectations requires engineers to think about the entire system, not just individual components.
Yes, I think it's a fair comparison. USB gave the industry a common way to connect devices, making technology easier to build and use. I see UCIe playing a similar role for chiplets. It gives semiconductor companies a common language to connect different chiplets, instead of reinventing the interface for every new design.
AI is changing the role of analog and mixed-signal engineers because power efficiency has become a system-level challenge rather than a circuit-level one. Early in my career, I learned that every milliwatt counts in chip design, because every efficiency improvement creates new opportunities for performance, functionality, and battery life. AI hardware raises the same challenge to a new level because every efficiency improvement creates more room for computing performance gains. That is why analog and mixed-signal design has become a bigger part of the overall architecture. Engineers now think beyond individual circuits and focus on how power delivery, signal quality, and high-speed communication work together to support the entire system.
That is a good question. Studying Electronics and Communication Engineering for my bachelor's degree and later earning a master's degree in Electrical Engineering gave me two different perspectives. My bachelor's program laid the foundation for my work in circuits, while graduate studies helped me think more deeply about system architecture and complex engineering problems. Serving as an evaluator for master's students in VLSI design and verification also gave me a chance to see how the next generation approaches these challenges. The students who stood out combined strong fundamentals with curiosity and a willingness to keep learning. Semiconductor technology changes quickly, so future engineers need more than technical knowledge. They need to understand how individual circuits fit into larger systems, adapt to new technologies, and keep asking the right questions.
I think the discussions at this year's IEEE/JSAP Symposium gave us a good picture of where the industry is heading. Over the next decade, chiplet architectures and UCIe will become a natural part of semiconductor design, while AI will help engineers solve increasingly complex problems.
For me, the most exciting part is that innovation will come from collaboration – between different technologies, different engineering disciplines, and people with new ideas. I believe that combination will define the next chapter of semiconductor design.