Google is reportedly developing a new server chip designed specifically to run its Gemini artificial intelligence models more efficiently. Informally called ‘Frozen v2,’ the chip could integrate elements of Gemini’s architecture directly into the hardware, according to a report by The Information.
The move highlights Google’s aim to build specialised infrastructure for its AI services. As demand for Gemini continues to rise, the tech giant is planning to generate more AI output while using less computing power and electricity.
The proposed chip could reduce the amount of data movement and number of processing decisions required during AI inference. These changes will help Google improve the efficiency of serving Gemini models to users.
According to the report, “Frozen v2 could deliver six to 10 times greater efficiency than Google’s latest custom AI chips when measured by the number of AI tokens generated per unit of power. Engineers are still working on the final design and deciding how much of the Gemini model architecture should be hardwired into the chip.”
Google may deploy the new chip as early as 2028, although the timeline could change as development continues. However, Google has yet to make any official statement. Alongside, Google's Frozen project is supposed to work along with its current Tensor Processing Units instead of replacing them. This means that Google could create its own family of chips for AI processing.
The reported chip development comes as Google faces mounting pressure over AI computing capacity. The growing demand for Gemini services has reportedly created internal strain and pushed Google Cloud to turn down some deals with external customers.
A semiconductor chip based on Gemini would allow Google to perform more AI tasks with fewer computing resources. This chip would also reduce the energy costs required for the generation of AI tokens.
Google’s overall strategy involves custom TPUs and other semiconductors developed in-house. The Frozen v2 version would be even more specialized by incorporating elements of the architecture into the chip.
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