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China’s Huawei Introduces ‘Tau Scaling Law’ to Challenge Moore’s Law in Chip Design

Huawei is exploring a new way to improve chip performance. The company introduced a new design idea termed the ‘Tau Scaling Law’ just when China is facing restrictions on advanced semiconductor tools.

Written By : Antara
Reviewed By : Sankha Ghosh

Huawei is working on a new chip design idea called the ‘Tau Scaling Law.’ For years, the chip-making industry has followed Moore’s Law. The idea suggested that chipmakers could place more transistors on processors every few years, helping devices become faster and more efficient. However, now, the Chinese chip giant has changed the rules of the game with this new approach.

The move comes as Chinese tech companies continue to face restrictions on advanced chipmaking technology from the United States and its allies.  Since 2019, China has been prohibited from importing ASML's most advanced extreme ultraviolet lithography machines. This curbed the domestic firm’s ability to chip-make and compete with global leaders like TSMC.

Huawei has reported that the method focuses on improving overall chip performance by enhancing speed, system design, and coordination between hardware and software.

Also Read: Apple Eyes Intel, Samsung to Break TSMC Reliance as Taiwan Tensions Rise

Reports suggest the company is trying to find new ways to improve processing power even without the latest manufacturing equipment. The approach could help Chinese firms continue building competitive chips despite restrictions.

The immediate debate sparked by this announcement is whether future Huawei chips will gobble up the market for TSMC chips. Regarding this, NVIDIA CEO Jensen Huang mentioned, “This is a breakthrough for Huawei, but it's not a threat for TSMC.” He further explained, “TSMC has been using die stacking and 3D packaging for how long now? Almost 10 years. And so TSMC's technology is very advanced.” 

The move may also increase global competition in the semiconductor industry. If Huawei’s approach proves effective, other companies may explore similar ideas rather than relying solely on traditional chip scaling. The latest development shows that the future of chip design may depend not only on smaller chips but also on smarter overall system performance.

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